The present application relates to semiconductor device fabrication, and more specifically to integration of vertical transistors and electrostatic discharge (ESD) diodes with increased junction areas.
As the advance of semiconductor technology, semiconductor devices are continually becoming more compact and circuit layouts are continually becoming more complex. As a result, semiconductor devices in circuits are more susceptible to burn-out by ESD events. ESD diodes are often required to prevent such burn-out. Since effectiveness of the protection provided by an ESD diode is associated with the junction area of the ESD diode, an ESD diode with larger junction area are desirable.
Vertical field effect transistors (FETs) are attractive candidates for 5 nm node and beyond due to better density scaling and better control of electrostatics. It is therefore desirable to have an improved structure and fabrication process for forming ESD diodes with increased junction areas that are compatible with the formation of vertical FETs.